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Implementation of Scheduling Algorithms for On Chip Communications

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Executive Summary

Network on Chips (NoCs) replace traditional busses in highly integrated MultiProcessor System on Chips (MPSoCs). As SoCs, communication issues take much important in NoCs but they need to give contention free architecture with low latency. To meet the above need several methods like handshaking mechanism and arbiter designs developed and implemented. This paper presents various scheduler designs using iSLIP scheduling algorithms and its comparative analysis with various arbiters. All the arbiters described using Verilog HDL and synthesized using Xilinx. For performance analysis, Cadence RTL compiler with UMC 0.13?m technology used to compute power and area of all the algorithms for arbiter.

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