Date Added: Dec 2012
In this paper, it is proposed to implement dynamically configurable serial communication block in Verilog. The developed module shall be interfaced with NIOS II soft processor as a general purpose IO port. The serial interface blocks shall be implemented to handle high data rate serial links and provide parallel interface to the processor. The Nios II IDE (EDK) shall be used for developing the test application in C programming language. The serial interface blocks which are coded in Verilog shall be synthesized using QUARTUS II EDA tool. The CYCLONE III family FPGA board shall be used for verifying the results on board.