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This paper describes a novel hardware scheme intended to realize future telecommunications satellite on-board digital processor performance targets, whilst meeting stringent power and mass constraints by using large ceramic substrates. The analysis takes a bottom-up approach, starting with trace geometry and substrate layer stack design, followed by architecture partitioning, trace routing capacity calculation, power distribution network analysis and surface budget estimation. The feasibility study, from which the work described in this paper is drawn, was completed in Spring 2006. Furthermore, the current substrate test piece design activity is briefly described and further work suggested. A mixture of Imperial and Metric units is used, as is common practice within the industry.
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