Improved Read Voltage Margins With Alternative Topologies for Memristor-Based Crossbar Memories
Memories based on hysteretic resistive materials are expected to have superior properties such as non-volatility, low power consumption, as well as very high capacity. Crossbar arrays are considered very attractive for future ultimately scaled memories. In this paper, the memristor-based passive crossbar geometry is studied and a set of different topological patterns, which introduce insulating junctions within the memory array, is presented. In the worst-case reading scenario the simulations revealed significantly improved sensed voltage margins which alleviate the rigorous requirement for large and high-performance CMOS sensing circuits in passive crossbar memory systems.