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Consider a processor organization consisting of a number of client modules and server modules (jointly called devices), like memory units and arithmetic-logic processing units. Suppose that these devices are interconnected with a bus which is segmented in such a way that devices connected to a particular segment can communicate in parallel to the data transfer operations going on in the other segments. This is achieved by a control logic which is able to reserve a continuous subsequence of the segments necessary to establish a path from the source to the target device.
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