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A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can insert the analyzer into a user design without manual labor required from the user. All processing is done on the VHDL-level, facilitating vendor-independent, source-level hardware debugging. The system also allows multiple independent FPGA-systems to be debugged in a single framework. Logic signal analyzers are very essential instrument for digital circuit or board debugging.
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