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Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level optimizations, such as Network-on-Chip (NoC) synthesis, are inaccurate in the presence of deep-submicron effects. In this paper, the authors propose new, highly accurate models for delay and power in buffered interconnects; these models are usable by system-level designers for existing and future technologies. They present a general and transferable methodology to construct their models from a wide variety of reliable sources (Liberty, LEF/ITF, ITRS and PTM). The modeling infrastructure, and a number of characterized technologies, are available as open source.
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