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HiperDispatch was introduced with IBM's z10 server, and is available (via PTFs) on z/OS V1R7, z/OS V1R8, and z/OS V1R9. HiperDispatch was designed to (1) minimize the z10 hardware performance degradation caused by processor cache misses, and (2) maximize the amount of CPU processing power associated with any single logical processor. To achieve these design objectives, HiperDispatch implemented new designs within z/OS and PR/SM, and implemented a regular exchange of information between PR/SM and z/OS. By exchanging information, z/OS is aware of the topology between logical processors and physical processors and PR/SM is aware of an affinity between workload executing on logical processors and the physical processors providing the processor capacity.
This paper provides an overview of the z10 implications that require HiperDispatch, explains the algorithms that existed before HiperDispatch, presents an introduction to HiperDispatach concepts, and describes performance considerations when implementing HiperDispatch.
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