Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-Bit Microcontroller Architecture
In this paper, the authors investigate the benefit of instruction set extensions for software implementations of all five SHA-3 candidates. To this end, they start from optimized assembly code for a common 16-bit microcontroller instruction set architecture. By themselves, these implementations provide reference for complexity of the algorithms on 16-bit architectures, commonly used in embedded systems. For each algorithm, they then propose suitable instruction set extensions and implement the modified processor core. They assess the gains in throughput, memory consumption, and the area overhead. Their results show that with less than 10% additional area, it is possible to increase the execution speed on average by almost 40%, while reducing memory requirements on average by more than 40%.