Processors

INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors

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Executive Summary

A multiprocessor's memory consistency model imposes ordering constraints among loads, stores, atomic operations, and memory fences. Even for consistency models that relax ordering among loads and stores, ordering constraints still induce significant performance penalties due to atomic operations and memory ordering fences. Several prior proposals reduce the performance penalty of strongly ordered models using post-retirement speculation, but these designs either maintain speculative state at a per-store granularity, causing storage requirements to grow proportionally to speculation depth, or employ distributed global commit arbitration using unconventional chunk-based invalidation mechanisms.

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