Date Added: Jan 2011
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results in a format (e.g. state graphs, bit vectors or signal waves) that remain disconnected from the real output of the application. The authors introduce in this paper the process of validation applied to digital designs in FPGAs.