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Nowadays, hardware devices are meant to host the execution of many complex, multi-core applications, whose functional and non-functional requirements vary according to the specific working domain. In this paper, the authors propose a design methodology that combines an efficient reconfigurable architecture and a related mapping flow. In particular, the proposed island-based hardware architecture couples an efficient area usage and an adaptable communication infrastructure. The proposed mapping flow distributes the cores on the device to optimize both performance and reconfiguration related metrics.
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