Storage

Lane Decoupling for Improving the Timing-Error Resiliency of Wide-SIMD Architectures

Free registration required

Executive Summary

A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guard-bands that ensure reliable execution. Timing speculation, where the pipeline operates at an unsafe voltage with any rare errors detected and resolved by the architecture, has been demonstrated to significantly improve the energy-efficiency of scalar processor designs. Unfortunately, applying the same timing-speculative approach to wide-SIMD architectures, such as those used in highly-efficient GPUs, may not provide similar gains. In this paper, the authors make two important contributions. The first is a set of models describing a parametrized general error probability function that is based on measurements of a fabricated chip and the expected efficiency benefits of timing speculation in a SIMD context.

  • Format: PDF
  • Size: 1064.96 KB