Date Added: Jun 2011
The authors explore using pulsed latches for timing optimization - a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. They exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as clock skew and retiming. They propose an algorithm that iteratively replaces certain flip-flops in a logic design with latches for an improvement in circuit speed. Results show that much of the performance improvement achieved by using multiple skewed clocks can also be achieved using a single clock and latches.