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LDPC Decoder for WiMAX Applications

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Executive Summary

In this paper, a memory based partially parallel Low Density Parity Check Decoder architecture for WiMAX applications is proposed to achieve good tradeoff between hardware complexity and decoding throughput. The block RAMs in the Field Programmable Gate Arrays (FPGA) are utilized to realize connectivity between Check Node Unit and Variable node Unit. The throughput can be increased linearly by increasing the parallelism with small additional hardware. Minsum decoding algorithm is used to decode the LDPC codes. The minsum algorithm is an approximation of the sum-product algorithm. From the perspective of implementation, the minsum algorithm requires lesser computations and lesser memory for storage. The decoder is synthesized with the tool Xilinx ISE 9.2 and implemented in the FPGA device XC5VLX220-2FF1760 and checked.

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