Leakage Reduction and Stability Improvement Techniques of 10T SRAM Cell: A Survey
High leakage currents on SRAM cell are the major contributor of total power consumption as the threshold voltage, channel length and gate oxide thickness. As technology scales down, the supply voltage, gate oxide thickness and channel length must be reduced. In future, the gate oxide thickness may be as low as 0.5nm for CMOS technologies. As a result, the reduction in gate oxide thickness increases gate leakage current. The gate tunneling current is also predicted to increase at a rate of 500 times per technology whereas the sub-threshold current increases by only 5 times.