Date Added: Feb 2010
In this paper, the authors examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. They present several design choices and focus on the power optimization of the NoC while achieving the required performance. They design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow timing constraints were used; they demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process. In order to evaluate the different alternatives, they report the synthesis results of a design that meets the actual throughput and timing requirements of the commercial SoC.