Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug
The authors propose new hardware and software techniques for FPGA functional debug that leverage the inherent re-configurability of the FPGA fabric to reduce functional debugging time. The functionality of an FPGA circuit is represented by a programming bit-stream that specifies the configuration of the FPGA's internal logic and routing. The proposed methodology allows different sets of design internal signals to be traced solely by changes to the programming bit-stream followed by device reconfiguration and hardware execution. Evidently, the advantage of this new methodology vs. existing debug techniques is that it operates without the need of iterative executions of the computationally-intensive design re-synthesis, placement and routing tools.