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Sequential decoding can achieve a very low computational complexity and short decoding delay when the Signal-to-Noise Ratio (SNR) is relatively high. In this paper, a low complexity high throughput decoding architecture based on a sequential decoding algorithm is proposed for convolutional codes. Parallel Fano decoders are scheduled to the code words in parallel input buffers according to buffer occupancy, so that the processing capabilities of the Fano decoders can be fully utilized, resulting in high decoding throughput. A Discrete Time Markov Chain (DTMC) model is proposed to analyze the decoding architecture. The relationship between the input data rate, the clock speed of the decoder and the input buffer size can be easily established via the DTMC model.
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