Low-Complexity High Throughput VLSI Architecture of Soft-Output ML MIMO Detector
In this paper VLSI architecture of a high throughput and high performance Soft-Output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. Maximum-Likelihood - ML - in the Max-Log sense) SO generation. A reduced complexity variant of the SO generation stage is also described. To the best of the authors' knowledge, the proposed architecture is the first VLSI implementation of a max-log ML MIMO detector which includes QR decomposition and SO generation, having the latter a deterministic very high throughput thanks to a fully parallelizable structure and parameterizability in terms of both the number of transmit and receive antennas, and the supported modulation orders.