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Hardware efficient, multi mode, re-configurable architecture of interleaver/de-interleaver for multiple standards, like DVB, WiMAX and WLAN is presented. The interleavers consume a large part of silicon area when implemented by using conventional methods as they use memories to store permutation patterns. In addition, different types of interleavers in different standards cannot share the hardware due to different construction methodologies. The novelty of the work presented in this paper is threefold: mapping of vital types of interleavers including convolutional interleaver onto a single architecture with flexibility to change interleaver size; hardware complexity for channel interleaving in WiMAX is reduced by using 2-D realization of the interleaver functions and silicon cost overheads reduced by avoiding the use of small memories.
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