Low-Current Probabilistic Writes for Power-Efficient STT-RAM Caches
MRAM has emerged as one of the most attractive non-volatile solutions due to fast read access, low leakage power, high bit density, and long endurance. However, the high power consumption of write operations remains a barrier to the commercial adoption of MRAM technology. This paper addresses this problem by introducing Low-Current Probabilistic Writes (LCPW), a technique that reduces write access energy by lowering the amplitude of the write current pulse. Although low current pulses no longer guarantee successful bit write operations, the authors propose and evaluate a simple technique to ensure correctness and achieve significant power reduction over a typical MRAM implementation.