Low Energy Mapping Technique for Hierarchical Network-on-Chip
Intellectual Property (IP) core-to-node mapping is an important but intractable optimization problem in Network-on-Chip (NoC) application design. In this paper, the authors present an approach to map cores onto hierarchical NoC architecture which consists of two levels. The top-level interconnection network is realized by a 2D mesh of communicating routers, and a tree based topology is used at the second level of interconnection hierarchy. They formulate the problem of low energy mapping, and introduce a three-phase optimization strategy to solve it. The cores are clustered firstly, and a tabu search based mapping technique is proposed to map the core clusters to the top-level interconnection network. Then the cores within each cluster are mapped to the nodes of every sub-network.