Processors

Low-Leakage Repeaters for NoC Interconnects

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Executive Summary

Several low-leakage repeater circuits for Network-on-Chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed Staggered-VT (SVT) repeater is compared with novel Dual-vT Domino (DTD) repeaters and Sleep Repeaters (SR). These circuits are compared with standard Low-VT (LVT) repeaters in a 32-bit link. Up to 70% and 61% power reduction was obtained in SVT and DTD repeaters, respectively. DTD repeaters are the most area-efficient ones, showing 40% reduction in total area of repeaters. Sleep Repeaters are most area consuming and less effective in high and moderate utilization rates, but comparable to SVT in terms of power for utilization rates below 2%, showing 72% power reduction.

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