Download now Free registration required
Network on-Chip (NoC) is a novel structural design template, which can be defied for complicated system level on-chip design. NoC has a potential to limit and present the bus-based communication. In this paper, the crisis to discuss is Low power consumption in an Asynchronous Network on-chip (NoC) level communication. NoC is implemented using FPGA which has less fabrication cost and reduces the complexity. An Asynchronous NoC has been implemented in Spartan kit using Xilinx FPGA ISE tools and its network interface is Advanced Microcontroller Bus Architecture (AMBA) which features numerous bus masters and a sole clock edge evolution and so on.
- Format: PDF
- Size: 1265.1 KB