Low Power and Improved Read Stability Cache Design in 45nm Technology
Cache is fastest memory which is played vital role in the present trend. Cache is achieved by SRAM. The scaling of CMOS technology has significant impact on SRAM cell - random fluctuation of electrical characteristics and substantial leakage current. In this paper, the authors proposed dynamic column based power supply 8T SRAM cell to improve the read stability and low leakage. In this paper, they compare the proposed SRAM cell with respect to conventional SRAM 6T in read mode. To verify read stability and write ability analysis they use N-curve metric. They extract RC parameters of conventional and proposed SRAM cell in read mode. They proved that proposed system is low power in a memory array.