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Low Power and Low Jitter Phase Frequency Detector for Phase Lock Loop

Date Added: Mar 2011
Format: PDF

In recent years, the design of low power and low jitter PLL for the different application has become one of the greatest challenges in high-performance Very Large Scale Integration (VLSI) design. As a consequence, many techniques have been introduced to minimize the power consumption and reduction in jitter of new VLSI circuits. Integrated Phase-Locked Loops (PLL's) play the versatile roles in the applications of clock generator, time synchronization and clock multiplication. A typical Phase Lock Loop architecture is depicted. It consists of a Phase Frequency Detector (PFD), a charge pump, a loop filter, a Voltage-Controlled Oscillator (VCO) and a frequency divider.