Low Power at Different Levels of VLSI Design and Clock Distribution Schemes

Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. In this paper various low power techniques at Gate level, Architecture level and different tradeoffs between different clock distribution schemes like as single driver clock scheme and distributed buffers clock scheme are reviewed. Here, it is also tried to showing various effects of particular clock distribution scheme such as clock skew, clock jitter, etc.

Provided by: International Journal of Computer Technology and Applications Topic: Hardware Date Added: Jan 2011 Format: PDF

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