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Driven by continued scaling of Moore's Law, the number of processing elements on a die is increasing dramatically. Recently there has been a surge of wide single instruction multiple data architectures designed to handle computationally intensive applications like 3D graphics, high definition video, image processing, and wireless communication. A limit of the SIMD width of these types of architectures is the scalability of the interconnect network between the processing elements in terms of both area and power. To mitigate this problem, the authors propose the use of a new interconnect topology, XRAM, which is a low-power high-performance matrix style crossbar.
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