Low Power Test Pattern Generation for BIST Applications
In this paper, the authors propose a novel Test Pattern Generator (TPG) for built-in self-test. Their method generates Multiple Single Input Change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences.