Download Now Free registration required
Network-on-Chip (NoC) architecture provides a high-performance communication infrastructure for system on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, the authors propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6?6, 8?8, and 10?10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively.
- Format: PDF
- Size: 473.2 KB