Maximizing MLC NAND Lifetime and Reliability in the Presence of Write Noise
The aggressive scaling of the NAND flash technology has led to write noise becoming the dominant source of disturbance in the currently shipping sub-30 nm MLC NAND memories. Write noise can be mitigated by reducing the magnitude of the voltage levels programmed into the cells, which additionally translates to longer flash memory lifetime. However, if all the target levels are small and close together, the probability of error could become excessively high. It is therefore necessary to optimize the target level placement in order to achieve a trade-off between flash lifetime and error probability.