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3D stacking of multi-core heterogeneous system opens a new era of architecture exploration with new partitioning of the overall System-on-Chip. After a description of the 3D stacking technologies, this paper reviews the existing memory interfaces and demonstrates that they need to evolve to new protocols in order to achieve the terabyte-per-second bandwidth with reasonable power consumption. 3D integration is a unique opportunity enabling memory-interconnect evolution to higher bandwidth. DRAM memory on processor vertical integration with wide data interconnects through TSVs is probably the most advanced scheme for providing high throughput memory connection.
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