Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches

Free registration required

Executive Summary

This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processor resources become constrained and error propensity increases. The continuing decrease in SRAM cell size and the growing capacity of caches increases the likelihood of errors in SRAM arrays. To address this, redundant information can be used to correct a value after an error occurs. Information redundancy is typically provided through Error-Correcting Codes (ECC), which append bits to every SRAM row and increase the array's area and energy consumption.

  • Format: PDF
  • Size: 1290.24 KB