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Reducing CPU frequency and voltage is a well-known approach to reduce the energy consumption of memory-bound applications. This is based on the conception that main memory performance sees little or no degradation at reduced processor clock speeds, while power consumption decreases significantly. The authors study this effect in detail on the latest generation of x86 64 compute nodes. Their results show that memory and last level cache bandwidths at reduced clock speeds strongly depend on the processor micro-architecture. For example, while an Intel Westmere-EP processor achieves 95% of the peak main memory bandwidth at the lowest processor frequency, the bandwidth decreases to only 60% on the latest Sandy Bridge-EP platform.
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