Hardware

Memory Subsystem Simulation in Software TLM/T Models

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Executive Summary

Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the memory subsystem accounts for up to 50%of the performance and energy expenditures, it has to be considered in system level design space exploration. In this paper, the authors present a novel technique to simulate memory accesses in software TLM/T models. The authors use a compiler to automatically expose all memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target memory addresses for accurate cache and memory simulation.

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