Microprocessor Cache Compression by Cellular Automata P-Match to Increase the Cache Capacity

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Executive Summary

Microprocessors speeds have been increasing faster than speed of off-chip memory. When multiprocessors are used in the system design, more processors require more accesses to memory. Thus raising a, 'Wall' between processor and memory. Accessing off-chip memory takes an order of magnitude more time than accessing an on-chip cache, two orders of magnitude more time than executing an instruction. Cache compression presents the challenge that the processor speed has to be improved but it should not substantially increase the total chip power consumption. This Cellular Automata (CA) based pattern matching architecture has number of novel features tailored for the application.

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