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Every successive technology node in the silicon manufacturing process timeline presents new and significant technical challenges. Historically, these challenges have been addressed head-on with the knowledge that increasingly dense FPGAs will always have buyers because of the steady demand created by Moore's Law across most industries. Military designers have traditionally spanned the entire space between "Early adopters" and "Followers" in design cycles by adopting more dense logic devices for size, weight, and power reduction, depending on the mission criticality of performance (and price sensitivity) of the digital logic in these designs. As silicon manufacturing technology moves ahead to each new and lower process technology node, a very careful risk decision must be made by both manufacturers, such as Altera, and digital designers.
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