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Parallelism is the key to continued performance scaling in modern microprocessors. Yet the authors observe that this parallelism can often contain a surprising amount of instruction redundancy. The authors propose to exploit this redundancy to improve performance and decrease energy consumption. They propose a multi-threading micro-architecture, Minimal Multi-Threading (MMT), that leverages register renaming and the instruction window to combine the fetch and execution of identical instructions between threads in SPMD applications. While many techniques exploit intra-thread similarities by detecting when a later instruction may use an earlier result, MMT exploits inter-thread similarities by, whenever possible, fetching instructions from different threads together and only splitting them if the computation is unique.
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