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Due to the continuous scaling of the MOS transistors it has become absolute necessary to investigate for the new transistor architectures for better control of SCEs and HCEs. In literature triple metal and double metal gate structure has been proposed to reduce the SCEs and HCEs due to scaling of the MOS transistors. The double metal and triple metal structures screen the effect of drain voltage change on the source/channel barrier reducing the SCE. The triple metal gate structure however induces an electrical junction on source and drain side which works as ultra shallow source/drain junctions.
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