Hardware

Modeling Shared Cache and Bus in Multi-Cores for Timing Analysis

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Executive Summary

Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this paper, the authors provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus. They also develop a cycle-accurate simulation infra-structure to evaluate the precision of the analysis. Experimental results from a large fragment of an in-orbit spacecraft software show that the analysis produces around 20% over-estimation over simulation results.

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