Modeling the Relationship Between FPGA Architecture and Place and Route Runtime

Free registration required

Executive Summary

This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. The authors consider both a simulated annealing based placement algorithm employing a bounding-box wire-length cost function, and a negotiation-based A router. They also show an example application of the model in early architecture evaluation. Since their introduction, Field-Programmable Gate Arrays (FPGAs) have continued to grow in both capacity and complexity. This scaling places increasing demands on the Accompanying Computer-Aided Design (CAD) tools. Compile times of an entire work day are now common.

  • Format: PDF
  • Size: 764.3 KB