Modular BiNoC Architecture Design for Network on Chip
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. Network on chip is efficient on chip communication architecture for SoC architecture. This paper presents a VHDL based model of a novel bidirectional channel network-on-chip BiNoC architecture to enhance the performance of on-chip communication.