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Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the application, systematic design methodology for various data transfer requirements is necessary. In this paper, the authors propose a new optimized bus design methodology under performance constraints. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to unoptimized architectures, their method can reduce the bus switch logic circuits significantly (by more than 50% sometimes).
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