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The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-Dimensional integration (3D), as well as Network-on-Chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for power-efficient application mapping onto 3D NoC-based devices. By clustering into the same router, IP cores with similar communication demands, it is possible to achieve reasonable energy savings while meeting timing constraints. Experimental results prove the efficiency of the proposed methodology since the authors achieve energy savings and temperature reduction up to 19% and 11%, respectively.
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