Multiplierless FIR Filter Implementation on FPGA
Area complexity in the algorithm of Finite Impulse Response (FIR) filter is mainly caused by multipliers. Among the multiplier-less techniques of FIR filter, Distributed Arithmetic is most preferred area efficient technique. In this technique, pre-computed values of inner product are stored in LUT, which are further added and shifted with number of iterations equal to the precision of input samples. But the exponential growth of LUT with the order of FIR filter, in its basic structure, makes it prohibitive for many applications.