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NBTI is an important emerging silicon reliability problem. In this paper the authors explore a microarchitecture-level approach to mitigate NBTI related failures in the functional units of a superscalar processor.They analyze the impact of dynamic instruction scheduling on NBTI and show that the conventional approach to instruction scheduling can accelerate the wear out of certain functional units. They then propose and evaluate two different NBTI-aware instruction scheduling policies and quantify the tradeoffs between performance and reliability of each policy.
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