Network Error Correction for Unit-Delay, Memory-Free Networks Using Convolutional Codes

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The core of a parallel processing system is the interconnection network by which the system's processors are linked. Due to the great role played by the interconnection network's topology in improving the parallel processing system's performance, various topologies have been proposed in the literature. This paper proposes a new interconnection network topology, referred to as the chained-cubic tree, in which chains of hypercubes are arranged in a tree structure. The major topological properties of the proposed topology have been investigated, including its diameter, degree, connectivity, bisection width, size, cost, and hamiltonicity.