Network-on-Chip Design Space Exploration: A PSO Based Integrated Approach
Network-on-Chip (NoC) has recently emerged as a communication solution for most of the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, the authors proposed a PSO based integrated design space exploration framework for the NoC design. The proposed design space exploration framework has two important steps i.e mapping and analytical modeling. In mapping phase, they mapped the target application onto a 2D mesh based architecture using Particle Swarm Optimization (PSO) based evolutionary algorithm technique. The objective of the mapping step is mainly to minimize the energy consumption. In the analytical modeling phase, a buffer allocation algorithm for wormhole routing based Networks-on-Chip is proposed.