Network-on-Chip Performance Evaluation by on-Chip Hardware Monitoring Network: OCP-IP Benchmarks on 48-core
The authors present in this paper a hardware monitoring network of reconfigurable traffic collector, which overcome the IO number limitation. The collectors in the monitoring network collect the statistic traffic information such as packet latency and throughput during the sampling time, and send them back through monitoring network to the off-chip memory for further analysis. Their 48-core Multi-Processor System on Chip (MPSoC) partitioned and implemented on a multi-FPGA platform is used in this study case. Hardware monitoring network is constructed on each FPGA to collect traffic information on the subpart of NoC. OCP-IP NoC benchmarks are used to measure the NoC performance.